As technology continues to advance at an unprecedented rate, the transfer of information or data has remained a high priority. In addition, as processing speeds continue to increase, the speed at which information is transferred remains key in increasing overall system speed. Traditionally, parallel busses or cables have been coupled between multiple devices to transfer information during a processing function. However, problems that may degrade the data transferred, such as signal loss when transmitted over long distances, have led to improvements in the manner in which such data is transferred. In addition, the multitude of wires or cables necessary for parallel connection may become cumbersome, especially in larger systems. In the past, however, alternatives to parallel connections often led to information bottlenecks, leaving parallel lines as the only viable choice.
As the need for bandwidth expands in the various networks now existing, or even those later developed, serial backplanes (or busses) have become the ideal alternative for solving these problems. Typically, serial backplanes employ a serializer at a transmitting end to convert and transmit data in serial order and a deserializer at a receiving end to convert the data back to parallel form once received. Such serializer/deserializer (“serdes”) receivers have become the benchmark for asynchronous communication and have provided clear advantages over parallel busses. For example, serdes receivers include transmitters and receivers, and use simplified wiring harnesses (often only a single wire per channel) that typically consume less power than their parallel-coupled counterparts. Higher performance may also be achieved because serdes receivers reduce the crosstalk that often occurs between parallel wires. In addition, serdes receivers may be employed to transmit data over long distances without the signal degradation experienced with parallel busses ultimately offering increased reliability and fidelity over parallel busses.
Although a tremendous improvement over parallel busses, serial connections employing serdes receivers are not without problems. Since a separate clock signal for component and signal synchronizing is not used (typical of asynchronous communication), the receiving and transmitting ends of a serdes are synchronized by monitoring the transmitted data. Within a conventional serial bus, each line of communication includes a separate serdes transceiver, each having a serdes receiver and transmitter, for serializing and deserializing each flume of data. As a result, each serdes receiver includes its own phase-locked loop (PLL) circuit, each typically employing a voltage controlled oscillator (VCO) to generate the clock at the receiving end of the data transmission and to synchronize the clock with the timing of the data signal at the transmitting end. Without this synchronization, the data transmitted would likely be corrupted or lost.
Among the more prominent problems typically found in conventional serial busses is the occurrence of crosstalk between VCOs in each of the serdes receivers. This crosstalk often results in skewed timing of the clocks, as well as jitter in the VCOs themselves. In addition, since each of the VCOs uses power to operate, the combined operation of multiple VCOs results in relatively large power consumption for the system.
Accordingly, what is needed in the art is a serdes receiver for use with a serial bus that does not suffer from the problems and deficiencies found in the prior art.